SH7080_09 Datasheet, PDF (805/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
Tables 15.4 to 15.6 show examples of SCBRR settings in asynchronous mode, and tables 15.7 to
15.9 show examples of SCBRR settings in clock synchronous mode.
Table 15.4 Bit Rates and SCBRR Settings in Asynchronous Mode (1)
Pφ (MHz)
Bit
Rate
(bits/s) n
10
Error
N (%)
12
nN
Error
(%)
14
nN
Error
(%)
16
nN
Error
(%)
18
nN
Error
(%)
20
nN
Error
(%)
110 2 177 -0.25 2 212 0.03 2 248 -0.17 3 70 0.03 3 79 -0.12 3 88 -0.25
150 2 129 0.16 2 155 0.16 2 181 0.16 2 207 0.16 2 233 0.16 3 64 0.16
300 2 64 0.16 2 77 0.16 2 90 0.16 2 103 0.16 2 116 0.16 2 129 0.16
600 1 129 0.16 1 155 0.16 1 181 0.16 1 207 0.16 1 233 0.16 2 64 0.16
1200 1 64 0.16 1 77 0.16 1 90 0.16 1 103 0.16 1 116 0.16 1 129 0.16
2400 0 129 0.16 0 155 0.16 0 181 0.16 0 207 0.16 0 233 0.16 1 64 0.16
4800 0 64 0.16 0 77 0.16 0 90 0.16 0 103 0.16 0 116 0.16 0 129 0.16
9600 0 32 -1.36 0 38 0.16 0 45 -0.93 0 51 0.16 0 58 -0.69 0 64 0.16
14400 0 21 -1.36 0 25 0.16 0 29 1.27 0 34 -0.79 0 38 0.16 0 42 0.94
19200 0 15 1.73 0 19 -2.34 0 22 -0.93 0 25 0.16 0 28 1.02 0 32 -1.36
28800 0 10 -1.36 0 12 0.16 0 14 1.27 0 16 2.12 0 19 -2.34 0 21 -1.36
31250 0 9 0.00 0 11 0.00 0 13 0.00 0 15 0.00 0 17 0.00 0 19 0.00
38400 0 7 1.73 0 9 -2.34 0 10 3.57 0 12 0.16 0 14 -2.34 0 15 1.73
Rev. 4.00 Dec. 15, 2009 Page 745 of 1558
REJ09B0181-0400