SH7080_09 Datasheet, PDF (99/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 2 CPU
2.5 Instruction Set
2.5.1 Instruction Set by Type
Table 2.10 lists the instructions classified by type.
Table 2.10 Instruction Types
Type
Data transfer
instructions
Arithmetic
operation
instructions
Kinds of
Instruction
5
21
Op Code Function
Number of
Instructions
MOV
Data transfer
39
Immediate data transfer
Peripheral module data transfer
Structure data transfer
MOVA
Effective address transfer
MOVT
T bit transfer
SWAP
Upper/lower swap
XTRCT Extraction of middle of linked registers
ADD
Binary addition
33
ADDC
Binary addition with carry
ADDV
Binary addition with overflow
CMP/cond Comparison
DIV1
Division
DIV0S
Signed division initialization
DIV0U
Unsigned division initialization
DMULS Signed double-precision multiplication
DMULU Unsigned double-precision multiplication
DT
Decrement and test
EXTS
Sign extension
EXTU
Zero extension
MAC
Multiply-and-accumulate, double-
precision multiply-and-accumulate
MUL
Double-precision multiplication
Rev. 4.00 Dec. 15, 2009 Page 39 of 1558
REJ09B0181-0400