SH7080_09 Datasheet, PDF (269/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.5.10 DTC Activation Priority Order
In the case where multiple DTC activation requests are generated while the DTC is inactive, it is
selectable whether the DTC starts transfer in the order of activation request generation or in the
order of priority for DTC activation. This selection is made by the setting of the DTPR bit in the
bus function extending register (BSCEHR). On the other hand, if multiple activation requests are
generated while the DTC is active, transfer is performed according to the priority order for DTC
activation. Figure 8.17 shows an example of DTC activation according to the priority.
(1) DTPR = 0
Internal bus
DTC is inactive
DTC is active
Transfer is started for the request
that is generated first
Transfer is performed according to the priority
Other than DTC
DTC (request 3) DTC (request 1) DTC (request 2)
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
Priority
determination
(2) DTPR =1
DTC is inactive
DTC is active
Transfer is performed according to the priority Transfer is performed according to the priority
Internal bus
Other than DTC
DTC (request 1) DTC (request 2) DTC (request 3)
DTC activation request 1
(High priority)
DTC activation request 2
(Medium priority)
DTC activation request 3
(Low priority)
Priority
determination
Priority
determination
Figure 8.17 Example of DTC Activation in Accordance with Priority
Rev. 4.00 Dec. 15, 2009 Page 209 of 1558
REJ09B0181-0400