SH7080_09 Datasheet, PDF (486/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.5.11 Number of Cycles per Access to On-Chip RAM by DMAC
The number of cycles required for read/write access to on-chip RAM from the DMAC is as shown
in table 10.9, which differs depending on the frequency ratio of Iφ (internal clock) to Bφ (external
bus clock).
Table 10.9 Number of Cycles per Access to On-Chip RAM by DMAC
Setting of Iφ:Bφ
Read
Write
1:1
3 × Bcyc
3 × Bcyc
1:1/2
2 × Bcyc
1 × Bcyc
1:1/3
2 × Bcyc
1 × Bcyc
1:1/4 or less
1 × Bcyc
1 × Bcyc
Notes: 1. Bcyc is the external bus clock cycle.
2. The number of cycles for access to the on-chip peripheral I/O or an external device are
indicated in section 9.5.16, Access to On-Chip Peripheral I/O Registers by CPU, and
section 9.5.17, Access to External Memory by CPU. The access cycles are obtained by
subtracting the cycles of Iφ required for L-bus access from the cycles required for
access by the CPU.
10.5.12 Note on DMAC Transfer in Burst Mode when Activation Source is MTU2
The corresponding bit among DMMTU4 to DMMTU0 in the bus function extending register
(BSCEHR) must be set when performing DMA transfer in burst mode with the MTU2 specified as
the activation source. For details, see section 9.4.8, Bus Function Extending Register (BSCEHR).
10.5.13 Bus Function Extending Register (BSCEHR)
With the bus function extending register (BSCEHR), it is possible to set the function to perform
transfer by the DMAC preferentially. For details, see section 9.4.8, Bus Function Extending
Register (BSCEHR).
Rev. 4.00 Dec. 15, 2009 Page 426 of 1558
REJ09B0181-0400