SH7080_09 Datasheet, PDF (360/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Ta1
Tadw
Ta2
Ta3
T1
Tw
Twx
T2
CK
A25 to A16
CSn
RDWR
AH
Read
RD
D15 to D0
Write
WRxx
D15 to D0
WAIT
BS
DACKn*
Address
Address
Data
Data
Note: * The waveform for DACKn is when active low is specified.
Figure 9.13 Access Timing for MPX Space
(Address Cycle Access Wait 1, Data Cycle Wait 1, External Wait 1)
Rev. 4.00 Dec. 15, 2009 Page 300 of 1558
REJ09B0181-0400