SH7080_09 Datasheet, PDF (302/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.4.1 Common Control Register (CMNCR)
CMNCR is a 32-bit register that controls the common items for each area.
Do not access external memory other than area 0 until the register initialization is complete.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
DMAIW[1:0] DMAIWA -
-
- HIZMEM HIZCNT
Initial value: 0
0
0
1
0
0
0
0
0
0
0
1
0
0
0
0
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R
R
R R/W R/W
Bit
Bit Name
31 to 13 ⎯
Initial
Value
All 0
12
⎯
1
11 to 8 ⎯
All 0
7, 6
DMAIW[1:0] 00
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R
Reserved
This bit is always read as 1. The write value should
always be 1.
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Wait Specification between Access Cycles during DMA
Single Address Transfer
Specify the number of idle cycles to be inserted after
data is output from an external device with DACK when
DMA single address transfer is performed. The method
of inserting idle cycles depends on the setting in the
DMAIWA bit described later.
00: No idle cycle inserted
01: 1 idle cycle inserted
10: 2 idle cycles inserted
11: 4 idle cycled inserted
Rev. 4.00 Dec. 15, 2009 Page 242 of 1558
REJ09B0181-0400