SH7080_09 Datasheet, PDF (649/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
(1) When buffer register is rewritten within one carrier cycle after the TGIA_3 interrupt
TGIA_3 interrupt generated
TGIA_3 interrupt generated
Buffer transfer-enabled
period
Bits 6 to 4 in TITCR
Bits 6 to 4 in TITCNT
Buffer register
Temporary register
General register
Buffer register rewrite timing
0
1
Data
Data
Data
Buffer register rewrite timing
2
2
0
Data1
Data1
Data1
1
Data2
Data2
Data2
(2) When buffer register is rewritten after one carrier cycle has elapsed after the TGIA_3 interrupt
TGIA_3 interrupt generated
TGIA_3 interrupt generated
Buffer transfer-enabled
period
Bits 6 to 4 in TITCR
Bits 6 to 4 in TITCNT
Buffer register
Temporary register
General register
Buffer register rewrite timing
0
Data
2
1
2
Data
Data
0
Data1
1
Data1
Data1
Note: Bits MD3 to MD0 in TMDR_3 are set to 1101, selecting buffer transfer at the crest. The skipping count
is set to two. T3AEN is set to 1, and T4VEN is cleared to 0.
Figure 11.77 Example of Operation when Buffer Transfer is Linked with Interrupt
Skipping (BTE1 = 1 and BTE0 = 0)
Rev. 4.00 Dec. 15, 2009 Page 589 of 1558
REJ09B0181-0400