SH7080_09 Datasheet, PDF (463/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
(1) When channel 0 transfers
Initial priority order _{CH0 > CH1 > CH2 > CH3}
Channel 0 becomes bottom
priority
Priority order
after transfer
CH1 > CH2 > CH3 > CH0
(2) When channel 1 transfers
Initial priority order
Priority order
after transfer
CH0 > CH1 > CH2 > CH3
CH2 > CH3 > CH0 > CH1
Channel 1 becomes bottom
priority.
The priority of channel 0, which
was higher than channel 1, is also
shifted.
(3) When channel 2 transfers
Initial priority order CH0 > CH1 > CH2 > CH3
Priority order
after transfer
CH3 > CH0 > CH1 > CH2
Post-transfer priority order
when there is an
immediate transfer
request to channel 1 only
CH2 > CH3 > CH0 > CH1
Channel 2 becomes bottom
priority.
The priority of channels 0 and 1,
which were higher than channel 2,
are also shifted. If immediately
after there is a request to transfer
channel 1 only, channel 1 becomes
bottom priority and the priority of
channels 3 and 0, which were
higher than channel 1, are also
shifted.
(4) When channel 3 transfers
Initial priority order _{CH0 > CH1 > CH2 > CH3}
Priority order
after transfer
CH0 > CH1 > CH2 > CH3
Priority order does not change.
Figure 10.3 Round-Robin Mode
Rev. 4.00 Dec. 15, 2009 Page 403 of 1558
REJ09B0181-0400