SH7080_09 Datasheet, PDF (869/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value R/W Description
0
DR
0
R/(W)* Receive Data Ready
Indicates that the number of data in the receive FIFO
data register (SCFRDR) is less than the specified
receive trigger number, and that the next data has not
yet been received after the elapse of 15 ETU from the
last stop bit in asynchronous mode. In clock
synchronous mode, this bit is not set to 1.
0: Receiving is in progress, or no receive data
remains in SCFRDR after receiving ended normally
[Clearing conditions]
• DR is cleared to 0 when the chip undergoes a
power-on reset
• DR is cleared to 0 when all receive data are read
after 1 is read from DR and then 0 is written
• DR is cleared to 0 when all receive data in
SCFRDR are read by the DTC
1: Next receive data has not been received
[Setting condition]
• DR is set to 1 when SCFRDR contains less data
than the specified receive trigger number, and the
next data has not yet been received after the
elapse of 15 ETU from the last stop bit.*
Note: * This is equivalent to 1.5 frames with the 8-bit,
1-stop-bit format. (ETU: Elementary time unit)
Note: * To clear the flag, only 0 can be written after reading 1.
Rev. 4.00 Dec. 15, 2009 Page 809 of 1558
REJ09B0181-0400