SH7080_09 Datasheet, PDF (1393/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 26 Power-Down Modes
Initial
Bit
Bit Name Value R/W Description
5
MSTP13 1
R/W Module Stop Bit 13
When this bit is set to 1, the supply of the clock to the
SCI_2 is halted.
0: SCI_2 operates
1: Clock supply to SCI_2 halted
4
MSTP12 1
R/W Module Stop Bit 12
When this bit is set to 1, the supply of the clock to the
SCI_1 is halted.
0: SCI_1 operates
1: Clock supply to SCI_1 halted
3
MSTP11 1
R/W Module Stop Bit 11
When this bit is set to 1, the supply of the clock to the
SCI_0 is halted.
0: SCI_0 operates
1: Clock supply to SCI_0 halted
2
MSTP10 1
R/W Module Stop Bit 10
When this bit is set to 1, the supply of the clock to the
SSU is halted.
0: SSU operates
1: Clock supply to SSU halted
1, 0
⎯
All 1
R Reserved
These bits are always read as 1. The write value should
always be 1.
26.3.4 Standby Control Register 4 (STBCR4)
STBCR4 is an 8-bit readable/writable register that controls the operation of modules in power-
down mode.
Bit: 7
6
5
4
MSTP MSTP MSTP
23
22
21
-
Initial value: 1
1
1
1
R/W: R/W R/W R/W R
3
2
1
0
-
MSTP MSTP MSTP
18
17
16
1
1
1
1
R R/W R/W R/W
Rev. 4.00 Dec. 15, 2009 Page 1333 of 1558
REJ09B0181-0400