SH7080_09 Datasheet, PDF (483/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
10.5.10 Notes on Using Peripheral Module Request Modes
When using a DMA transfer for which A/D_1 (ADI_1), SCI_0 (TXI_0), SCI_0 (RXI_0), SCI_1
(TXI_1), or SCI_1 (RXI_1) is selected as the transfer request source, any interrupt requests from
the peripheral module selected as the transfer request source are accepted and held as DMA
transfer requests. As a result, a DMA transfer may occur in the absence of a DMA transfer request
when one of the following conditions is met:
1. When A/D_1 (ADI_1), SCI_0 (TXI_0), SCI_0 (RXI_0), SCI_1 (TXI_1), or SCI_1 (RXI_1) is
selected as the DMA transfer request source after an interrupt request (ADI_1, TXI_0, RXI_0,
TXI_1, or RXI_1) was generated and the interrupt source flag (ADF in ADCSR, TDRE or
RDRF in SCSSR) was cleared by the CPU or DTC.
2. When the interrupt source flag (ADF in ADCSR, TDRE or RDRF in SCSSR) is cleared by the
CPU after A/D_1 (ADI_1), SCI_0 (TXI_0), SCI_0 (RXI_0), SCI_1 (TXI_1), or SCI_1
(RXI_1) was selected as the DMA transfer request source.
3. When DMA transfers are enabled (DE = 1) while interrupts are disabled (ADIE = 0 in
ADCSR, TIE = 0 or RIE = 0 in SCSCR) for the peripheral module selected as the DMA
transfer request source.
This problem can be avoided by using one of the following workarounds:
1. When SCI_0 (TXI_0) or SCI_1 (TXI_1) is the transfer request source
⎯ Enable DMA transfers (DE = 1) after confirming that the transmit data empty interrupt (TE
= 1 and TIE = 1 in SCSCR and TDRE = 1 in SCSSR) has been generated.
2. When A/D_1 (ADI_1), SCI_0 (RXI_0), or SCI_1 (RXI_1) is the transfer request source
⎯ Before using a DMA transfer, do not use a CPU interrupt or DTC transfer that uses the
same interrupt request.
⎯ Only clear the interrupt source flag (ADF in ADCSR or RDRF in SCSSR) by a DMA
transfer. Do not clear it by the CPU or DTC. When it is necessary to clear the interrupt
source flag, perform one (dummy) DMA transfer while operation of the peripheral module
is disabled (ADST = 0 in ADCR or RE = 0 in SCSCR).
⎯ Enable DMA transfers (DE = 1) after enabling the interrupt request (ADIE = 1 in ADCSR
or RIE = 1 in SCSCR).
Figure 10.22 shows an example DMA transfer sequence when SCI_0 (RXI_0) or SCI_1 (RXI_1)
is selected as the transfer request source, and figure 10.23 shows an example dummy transfer
sequence.
Rev. 4.00 Dec. 15, 2009 Page 423 of 1558
REJ09B0181-0400