SH7080_09 Datasheet, PDF (887/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name value
R/W Description
2
SCKDT Undefined R/W SCK Port Data
Controls the SCK pin in combination with the SCKIO bit
in this register, the C/A bit in SCSMR, and bits CKE1
and CKE0 in SCSCR. Select the SCK pin function in
the PFC (pin function controller) beforehand.
C/A CKE1 CKE0 SCKIO SCKDT: SCK pin state
00 0
0
×:
Setting prohibited
(initial state)
00 0
1
0:
Low level output
00 0
1
1:
High level output
00 1
×
×:
Internal clock output
according to serial core
logic
01 0
×
×:
External clock input to
serial core logic
01 1
×
×:
Setting prohibited
10 0
×
×:
Internal clock output
according to serial core
logic
10 1
×
×:
Internal clock output
according to serial core
logic
11 0
×
×:
External clock input to
serial core logic
11 1
×
×:
Setting prohibited
Note: ×: Don't care
1
SPBIO 0
R/W Serial Port Break Output Control
Controls the TXD pin in combination with the SPBDT bit
in this register and the TE bit in SCSCR.
0
SPBDT Undefined R/W Serial Port Break Data
Controls the TXD pin in combination with the SPBIO bit
in this register and the TE bit in SCSCR. Select the
TXD pin function in the PFC (pin function controller)
beforehand.
TE SPBIO SPBDT: TXD pin state
00
×:
Setting prohibited (initial state)
01
0:
Low level output
01
0×
1:
High level output
×:
Transmit data output according
to serial core logic
Note: ×: Don't care
Rev. 4.00 Dec. 15, 2009 Page 827 of 1558
REJ09B0181-0400