SH7080_09 Datasheet, PDF (217/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
7.3.14 Branch Destination Register (BRDR) (Only in F-ZTAT Version)
BRDR is a 32-bit read-only register. BRDR stores bits 27 to 0 in the address of the branch
destination instruction. BRDR has the flag bit that is set to 1 when a branch occurs. This flag bit is
cleared to 0 when BRDR is read, the setting to enable PC trace is made, or BRDR is initialized by
a power-on reset or a manual reset. Other bits are not initialized by a power-on reset. The four
BRSR registers (eight pairs for the F-ZTAT version supporting full functions of E10A) have a
queue structure and a stored register is shifted at every branch.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DVF
-
-
- BDA27 BDA26 BDA25 BDA24 BDA23 BDA22 BDA21 BDA20 BDA19 BDA18 BDA17 BDA16
Initial value: 0
0
0
0
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BDA15 BDA14 BDA13 BDA12 BDA11 BDA10 BDA9 BDA8 BDA7 BDA6 BDA5 BDA4 BDA3 BDA2 BDA1 BDA0
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31
DVF
30 to 28 ⎯
27 to 0 BDA27 to
BDA0
Initial
Value R/W
0
R
All 0
R
Undefined R
Description
BRDR Valid Flag
Indicates whether a branch destination address is
stored. This flag bit is set to 1 when a branch occurs.
This flag is cleared to 0 when BRDR is read, the
setting to enable PC trace is made, or BRDR is
initialized by a power-on reset.
0: The value of BRDR register is invalid
1: The value of BRDR register is valid
Reserved
These bits are always read as 0. The write value
should always be 0.
Branch Destination Address
Store bits 27 to 0 of the branch destination address.
Rev. 4.00 Dec. 15, 2009 Page 157 of 1558
REJ09B0181-0400