SH7080_09 Datasheet, PDF (1020/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 19 A/D Converter (ADC)
Bit
3 to 0
Bit Name
TRG0S[3:0]
Initial
Value
0000
[Legend]
x: Don't care
R/W Description
R/W A/D Trigger 0 Select 3 to 0
Select an external trigger, MTU2 trigger, or MTU2S
trigger to start A/D conversion for A/D module 0. In 2-
channel scan mode, these bits select an external
trigger, MTU2 trigger, or MTU2S trigger to start A/D
conversion for group 0.
0000: External trigger pin (ADTRG) input
0001: TGRA input capture/compare match on each
MTU2 channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
0010: MTU2 CH0 compare match (TRG0N)
0011: MTU2 A/D conversion start request delaying
(TRG4AN)
0100: MTU2 A/D conversion start request delaying
(TRG4BN)
0101: TGRA input capture/compare match on each
MTU2S channel or TCNT_4 trough in
complementary PWM mode (TRGAN)
0110: Setting prohibited
0111: MTU2S A/D conversion start request delaying
(TRG4AN)
1000: MTU2S A/D conversion start request delaying
(TRG4BN)
1001: Setting prohibited
101x: Setting prohibited
11xx: Setting prohibited
When switching the selector, first clear the ADST bit in
the A/D control register (ADCR) to 0.
Specify different trigger sources for the group 0 and
group 1 conversion requests so that a group 0
conversion request is not generated simultaneously
with a group 1 conversion request in 2-channel scan
mode.
Rev. 4.00 Dec. 15, 2009 Page 960 of 1558
REJ09B0181-0400