SH7080_09 Datasheet, PDF (323/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
1, 0
WTRC[1:0] 00
R/W Number of Idle Cycles from REF Command
Issuance/Exit from Self-Refresh Mode until
ACTV/REF/MRS Command Issuance
Specify the minimum number of idle cycles between
commands in the following cases.
• From issuance of REF command to issuance of
ACTV/REF/MRS command.
• From exit from self-refresh mode to issuance of
ACTV/REF/MRS command.
The setting for areas 2 and 3 is common.
00: 2 cycles
01: 3 cycles
10: 5 cycles
11: 8 cycles
(5) PCMCIA
• CS5WCR, CS6WCR
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
SA[1:0]
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
-
TED[3:0]
PCW[3:0]
WM
-
Initial value: 0
0
0
0
0
1
0
1
0
0
0
R/W: R R/W R/W R/W R/W R/W R/W R/W R/W R/W R
4
3
2
1
0
-
TEH[3:0]
0
0
0
0
0
R R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 22 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 4.00 Dec. 15, 2009 Page 263 of 1558
REJ09B0181-0400