SH7080_09 Datasheet, PDF (74/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 1 Overview
Classification
System control
Interrupts
Address bus
Data bus
Symbol
I/O
RES
I
MRES
I
WDTOVF O
BREQ
I
BACK
O
NMI
I
IRQ7 to IRQ0 I
IRQOUT
O
A29 to A0 O
D31 to D0 I/O
Name
Function
Power-on reset When low, this LSI enters the power-
on reset state.
Manual reset
When low, this LSI enters the
manual reset state.
Watchdog timer
overflow
Output signal for the watchdog timer
overflow. If this pin need to be pulled
down, use the resistor larger than
1 MΩ to pull this pin down.
Bus-mastership
request
Low when an external device
requests the release of the bus
mastership.
Bus-mastership
request
acknowledge
Indicates that the bus mastership
has been released to an external
device. Reception of the BACK
signal informs the device which has
output the BREQ signal that it has
acquired the bus.
Non-maskable
interrupt
Non-maskable interrupt request pin.
Fix to high or low level when not in
use.
Interrupt requests Maskable interrupt request pin.
7 to 0
Selectable as level input or edge
input. The rising edge, falling edge,
and both edges are selectable as
edges.
Interrupt request
output
Shows that an interrupt cause has
occurred. The interrupt cause can be
recognized even in the bus release
state.
Address bus
Outputs addresses.
A24 to A0 are available in the
SH7083.
A25 to A0 are available in the
SH7084/SH7085.
Data bus
32-bit bidirectional bus.
D15 to D0 are available in the
SH7083/SH7084.
Rev. 4.00 Dec. 15, 2009 Page 14 of 1558
REJ09B0181-0400