SH7080_09 Datasheet, PDF (219/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
7.4.2 User Break on Instruction Fetch Cycle
1. When L bus/instruction fetch/read/word, longword, or not including the operand size is set in
the break bus cycle register (BBRA or BBRB), the break condition becomes the L bus
instruction fetch cycle. Whether it breaks before or after the execution of the instruction can
then be selected with the PCBA or PCBB bit in the break control register (BRCR) for the
appropriate channel. If an instruction fetch cycle is set as a break condition, clear LSB in the
break address register (BARA or BARB) to 0. A user break cannot be generated as long as this
bit is set to 1.
2. If the break condition matches when a user break on instruction fetch is specified so that the a
break is generated before the execution of the instruction, the user break is generated at the
point when it has become deterministic that the instruction will be executed after it is fetched.
This means this feature cannot be used on instructions fetched by overrun (instructions fetched
at a branch or during an interrupt transition, but not to be executed). When this kind of break
condition is set for the delay slot of a delayed branch instruction, the user break is generated
prior to execution of the delayed branch instruction.
Note: If a branch does not occur at a delay condition branch instruction, the subsequent
instruction is not recognized as a delay slot.
3. When the break condition is specified so that a user break is generated after execution of the
instruction, the instruction that has met the break condition is executed and then the user break
is generated before the next instruction is executed. As with pre-execution user breaks, this
cannot be used with overrun fetch instructions. When this kind of break condition is set for a
delayed branch instruction and its delay slot, a user break is not generated until the first
instruction at the branch destination.
4. When an instruction fetch cycle is set, the break data register (BDRA or BDRB) is ignored.
Therefore, break data cannot be set for the user break of the instruction fetch cycle.
5. If the I bus is set for a user break of an instruction fetch cycle, the condition is determined for
the instruction fetch cycles on the I bus. For details, see 5 in section 7.4.1, Flow of the User
Break Operation.
Rev. 4.00 Dec. 15, 2009 Page 159 of 1558
REJ09B0181-0400