SH7080_09 Datasheet, PDF (842/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
Table 15.17 SCI Interrupt Sources
Interrupt Source
ERI
RXI
TXI
TEI
Description
Interrupt caused by receive error (ORER, FER, or
PER)
Interrupt caused by receive data full (RDRF)
Interrupt caused by transmit data empty (TDRE)
Interrupt caused by transmit end (TENT)
DMAC/DTC Activation
Not possible
Possible
Possible
Not possible
15.6 Serial Port Register (SCSPTR) and SCI Pins
The relationship between SCSPTR and the SCI pins is shown in figures 15.19 and 15.20.
SCK
Reset
R
QD
SCKIO
C
Bit 3
SPTRW
Reset
R
QD
SCKDT
C
Bit 2
SPTRW
Internal data bus
Clock output enable signal*
Serial clock output signal*
Serial clock input signal*
Serial input enable signal*
[Legend]
SPTRW: SCSPTR write
Note: * These signals control the SCK pin according to the settings of the C/A bit in SCSMR
and bits CKE1 and CKE0 in SCSCR.
Figure 15.19 SCKIO Bit, SCKDT bit, and SCK Pin
Rev. 4.00 Dec. 15, 2009 Page 782 of 1558
REJ09B0181-0400