SH7080_09 Datasheet, PDF (11/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

5.5.2 Trap Instructions ..................................................................................................... 97
5.5.3 Illegal Slot Instructions ........................................................................................... 98
5.5.4 General Illegal Instructions..................................................................................... 98
5.6 Cases when Exceptions are Accepted .................................................................................. 99
5.7 Stack States after Exception Handling Ends ...................................................................... 100
5.8 Usage Notes ....................................................................................................................... 102
5.8.1 Value of Stack Pointer (SP) .................................................................................. 102
5.8.2 Value of Vector Base Register (VBR) .................................................................. 102
5.8.3 Address Errors Caused by Stacking for Address Error Exception Handling ........ 102
5.8.4 Notes on Slot Illegal Instruction Exception Handling .......................................... 103
Section 6 Interrupt Controller (INTC) ...............................................................105
6.1 Features.............................................................................................................................. 105
6.2 Input/Output Pins ............................................................................................................... 107
6.3 Register Descriptions ......................................................................................................... 108
6.3.1 Interrupt Control Register 0 (ICR0)...................................................................... 109
6.3.2 IRQ Control Register (IRQCR) ............................................................................ 110
6.3.3 IRQ Status register (IRQSR) ................................................................................ 113
6.3.4 Interrupt Priority Registers A to F and H to M (IPRA to IPRF and IPRH to IPRM)118
6.4 Interrupt Sources................................................................................................................ 121
6.4.1 External Interrupts ................................................................................................ 121
6.4.2 On-Chip Peripheral Module Interrupts ................................................................. 122
6.4.3 User Break Interrupt ............................................................................................. 122
6.5 Interrupt Exception Handling Vector Table....................................................................... 123
6.6 Interrupt Operation............................................................................................................. 127
6.6.1 Interrupt Sequence ................................................................................................ 127
6.6.2 Stack after Interrupt Exception Handling ............................................................. 130
6.7 Interrupt Response Time.................................................................................................... 130
6.8 Data Transfer with Interrupt Request Signals .................................................................... 132
6.8.1 Handling Interrupt Request Signals as Sources for DTC Activation and
CPU Interrupts, but Not DMAC Activation ......................................................... 133
6.8.2 Handling Interrupt Request Signals as Sources for DMAC Activation,
but Not CPU Interrupts and DTC Activation........................................................ 134
6.8.3 Handling Interrupt Request Signals as Sources for DTC Activation,
but Not CPU Interrupts and DMAC Activation.................................................... 134
6.8.4 Handling Interrupt Request Signals as Sources for CPU Interrupts,
but Not DTC and DMAC Activation.................................................................... 134
6.9 Usage Note......................................................................................................................... 134
Rev. 4.00 Dec. 15, 2009 Page ix of lviii
REJ09B0181-0400