SH7080_09 Datasheet, PDF (429/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.34 Minimum Number of Idle Cycles between Access Cycles of the DMAC Single
Address Mode for the SDRAM Interface (2)
Transfer from the SDRAM interface to the external device with DACK
BSC Register Setting*
CS3BCR Idle Setting
CS3WCR.WTRP Setting
Minimum Number of
Idle Cycles
0
1
3
0
2
3
0
3
3
0
4
4
1
1
3
1
2
3
1
3
3
1
4
4
2
1
3
2
2
3
2
3
3
2
4
4
4
1
5
4
2
5
4
3
5
4
4
5
Notes: DMAC is driven by Bφ. The minimum number of idle cycles is not affected by changing a
clock ratio.
* Other than the following cases.
Single address mode transfer from the external device with DACK to the SDRAM
interface, where the minimum number of idle cycles is not affected by the IWW,
IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR.
CMNCR.DMAIWA = 0, where the setting is identical to CMNCR.DMAIW[1:0] in table
9.33.
Rev. 4.00 Dec. 15, 2009 Page 369 of 1558
REJ09B0181-0400