SH7080_09 Datasheet, PDF (383/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Single Write: A write access ends in one cycle when the data bus width is larger than or equal to
access size. This is called single write.
Figure 9.21 shows the single write basic timing.
CK
A25 to A0
A12/A11*¹
CSn
RASL, RASU
CASL, CASU
RDWR
DQMxx
D31 to D0
BS
DACKn*²
Tr
Tc1 Trwl
Tap
Notes: 1. Address pin to be connected to pin A10 of SDRAM.
2. The waveform for DACKn is when active low is specified.
Figure 9.21 Single Write Basic Timing (Auto-Precharge)
Bank Active: The SDRAM bank function is used to support high-speed accesses to the same row
address. When the BACTV bit in SDCR is 1, accesses are performed using commands without
auto-precharge (READ or WRIT). This function is called bank-active function. This function is
valid only for area 3. When area 3 is set to bank-active mode, area 2 should be set to normal space
or SRAM with byte selection. When areas 2 and 3 are both set to SDRAM, auto-precharge mode
must be set.
In this case, precharging is not performed when the access ends. When accessing the same row
address in the same bank, it is possible to issue the READ or WRIT command immediately,
without issuing an ACTV command. As SDRAM is internally divided into several banks, it is
possible to activate one row address in each bank. If the next access is to a different row address, a
PRE command is first issued to precharge the relevant bank, then when precharging is completed,
Rev. 4.00 Dec. 15, 2009 Page 323 of 1558
REJ09B0181-0400