SH7080_09 Datasheet, PDF (419/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Table 9.29 Minimum Number of Idle Cycles between CPU Access Cycles in Normal Space
Interface
BSC Register Setting
When Access Size is Less than
Bus Width
When Access Size Exceeds Bus Width
Contin- Contin-
CSnWCR. CSnBCR Read to Write to Read to Write to uous uous Read to Write to Read to Write to
WM Setting Idle Setting Read Write Write Read Read*¹ Write*¹ Read*² Write*² Write*² Read*²
1
0
1/1/1/1 0/0/0/0 3/3/3/4 0/0/0/0 0/0/0/0 0/0/0/0 1/1/1/1 0/0/0/0 3/3/3/4 0/0/0/0
0
0
1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1
1
1
1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1
0
1
1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 1/1/1/1 3/3/3/4 1/1/1/1
1
2
2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2
0
2
2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 2/2/2/2 3/3/3/4 2/2/2/2
1
4
4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4
0
4
4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4 4/4/4/4
Notes: The minimum numbers of idle cycles are described sequentially for Iφ:Bφ = 4:1, 3:1, 2:1,
and 1:1.
1. Minimum number of idle cycles between the word access to address 0 and the word
access to address 2 in the 32-bit access with a 16-bit bus width,
minimum number of idle cycles between the byte access to address 0 and the byte
access to address 1 in the 16-bit access with an 8-bit bus width,
minimum number of idle cycles between the byte accesses to address 0, to address 1,
to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and
minimum number of idle cycles between consecutive accesses in 16-byte transfer.
2. Other than the above cases
Rev. 4.00 Dec. 15, 2009 Page 359 of 1558
REJ09B0181-0400