SH7080_09 Datasheet, PDF (1010/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 19 A/D Converter (ADC)
19.3.2 A/D Control/Status Registers_0 to _2 (ADCSR_0 to ADCSR_2)
ADCSR for each module controls A/D conversion operations.
Bit: 15 14 13
ADF ADIE -
Initial value: 0
0
0
R/W:R/(W)* R/W R
12 11 10 9
8
7
6
5
4
3
2
1
0
- TRGE - CONADF STC
CKSL[1:0]
ADM[1:0] ADCS
CH[2:0]
0
0
0
0
0
0
0
0
0
0
0
0
0
R R/W R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Note: * Writing 0 to this bit after reading it as 1 is clears the flag and is the only allowed way.
Initial
Bit Bit Name Value
15
ADF
0
14
ADIE
0
13, 12 ⎯
All 0
R/W
R/(W)*
R/W
R
Description
A/D End Flag
A status flag that indicates the end of A/D conversion.
[Setting conditions]
• When A/D conversion ends in single mode
• When A/D conversion ends on all specified
channels in scan mode
[Clearing conditions]
• When 0 is written after reading ADF = 1
• When the DMAC is activated by an ADI interrupt
and ADDR is read
• When the DTC is activated by an ADI interrupt and
ADDR is read while the DISEL bit in the MRB
register of the DTC is cleared to 0
A/D Interrupt Enable
The A/D conversion end interrupt (ADI) request is
enabled when 1 is set
When changing the operating mode, first clear the
ADST bit to 0.
Reserved
These bits are always read as 0. The write value
should always be 0.
Rev. 4.00 Dec. 15, 2009 Page 950 of 1558
REJ09B0181-0400