SH7080_09 Datasheet, PDF (237/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.2.3 DTC Source Address Register (SAR)
SAR is a 32-bit register that designates the source address of data to be transferred by the DTC.
SAR cannot be accessed directly from the CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
* : Undefined
8.2.4 DTC Destination Address Register (DAR)
DAR is a 32-bit register that designates the destination address of data to be transferred by the
DTC.
DAR cannot be accessed directly from the CPU.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
* : Undefined
Rev. 4.00 Dec. 15, 2009 Page 177 of 1558
REJ09B0181-0400