SH7080_09 Datasheet, PDF (681/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
Status Flag Clearing Timing: After a status flag is read as 1 by the CPU, it is cleared by writing
0 to it. When the DTC/DMAC is activated, the flag is cleared automatically. Figures 11.115 and
11.116 show the timing for status flag clearing by the CPU, and figures 11.117 to 11.119 show the
timing for status flag clearing by the DTC/DMAC.
MPφ, Pφ
TSR write cycle
T1
T2
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 11.115 Timing for Status Flag Clearing by CPU (Channels 0 to 4)
MPφ, Pφ
TSR write cycle
T1
T2
Address
TSR address
Write signal
Status flag
Interrupt
request signal
Figure 11.116 Timing for Status Flag Clearing by CPU (Channel 5)
Rev. 4.00 Dec. 15, 2009 Page 621 of 1558
REJ09B0181-0400