SH7080_09 Datasheet, PDF (1390/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 26 Power-Down Modes
26.3 Register Descriptions
There are following registers used for the power-down modes. For details on the addresses of
these registers and the states of these registers in each processing state, see section 27, List of
Registers.
Table 26.3 Register Configuration
Register Name
Standby control register 1
Standby control register 2
Standby control register 3
Standby control register 4
Standby control register 5
Standby control register 6
RAM control register
Abbrevia-
tion
R/W Initial Value Address
Access Size
STBCR1 R/W H'00
H'FFFFE802 8
STBCR2 R/W H'38
H'FFFFE804 8
STBCR3 R/W H'FF
H'FFFFE806 8
STBCR4 R/W H'FF
H'FFFFE808 8
STBCR5 R/W H'03
H'FFFFE80A 8
STBCR6 R/W H'00
H'FFFFE80C 8
RAMCR R/W H'10
H'FFFFE880 8
26.3.1 Standby Control Register 1 (STBCR1)
STBCR1 is an 8-bit readable/writable register that specifies the state of the power-down mode.
Bit: 7
6
5
4
3
2
1
0
STBY -
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R/W R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
7
STBY
0
R/W Standby
Specifies transition to software standby mode.
0: Executing SLEEP instruction makes this LSI sleep
mode
1: Executing SLEEP instruction makes this LSI software
standby mode or deep software standby mode
Rev. 4.00 Dec. 15, 2009 Page 1330 of 1558
REJ09B0181-0400