SH7080_09 Datasheet, PDF (1383/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 24 Mask ROM
Section 24 Mask ROM
This LSI is available with 256 Kbytes of on-chip mask ROM. The on-chip ROM is connected to
the CPU, direct memory access controller (DMAC), and data transfer controller (DTC) through a
32-bit data bus (figure 24.1). The CPU, DMAC, and DTC can access the on-chip ROM in 8, 16
and 32-bit widths. Data in the on-chip ROM can always be accessed in one cycle.
Internal data bus (32 bits)
H'00000000
H'00000004
H'00000001
H'00000005
H'00000002
H'00000006
H'00000003
H'00000007
On-chip ROM
H'0003FFFC
H'0003FFFD
H'0003FFFE
H'0003FFFF
Figure 24.1 Mask ROM Block Diagram
The operating mode determines whether the on-chip ROM is valid or not. The operating mode is
selected using mode-setting pins FWE, MD1, and MD0. If you are using the on-chip ROM, select
mode 2 or mode 3; if you are not, select mode 0 or 1. The on-chip ROM is allocated to addresses
H'00000000 to H'0003FFFF of memory area 0.
RAM0200A_010020030800
Rev. 4.00 Dec. 15, 2009 Page 1323 of 1558
REJ09B0181-0400