SH7080_09 Datasheet, PDF (455/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value
9, 8 PR[1:0] 00
7 to 3 —
All 0
2
AE
0
R/W Description
R/W Priority Mode 1, 0
Select the priority level between channels when there are
transfer requests for multiple channels simultaneously.
00: CH0 > CH1 > CH2 > CH3
01: CH0 > CH2 > CH3 > CH1
10: Setting prohibited
11: Round-robin mode
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/(W)* Address Error Flag
Indicates that an address error occurred during DMA
transfer. If this bit is set, DMA transfer is disabled even if
the DE bit in CHCR and the DME bit in DMAOR are set to
1. This bit can only be cleared by writing 0 after reading
1.
0: No DMAC address error
[Clearing condition]
• Writing AE = 0 after AE = 1 read
1: DMAC address error occurs
Rev. 4.00 Dec. 15, 2009 Page 395 of 1558
REJ09B0181-0400