SH7080_09 Datasheet, PDF (425/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
BSC Register Setting
CPU Access
DMAC or DTC
Access
CSnBCR CS3WCR. CS3WCR.
Idle
WTRP TRWL Read to Write to Read to Write to Read to Write to
Setting Setting Setting Read
Write
Write
Read
Write Read
4
2
2
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
2
3
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
3
0
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
3
1
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
3
2
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
3
3
5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5
5
4
4
0
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
4
1
5/5/5/5 4/4/4/4 5/5/5/5 4/4/4/4 5
4
4
4
2
5/5/5/5 5/5/5/5 5/5/5/5 5/5/5/5 5
5
4
4
3
5/5/5/5 6/6/6/6 5/5/5/5 6/6/6/6 5
6
Note:
The minimum numbers of idle cycles in CPU Access are described sequentially for Iφ:Bφ =
4:1, 3:1, 2:1, and 1:1.
DMAC and DTC are driven by Bφ. The minimum number of idle cycles is not affected by
changing a clock ratio.
Rev. 4.00 Dec. 15, 2009 Page 365 of 1558
REJ09B0181-0400