SH7080_09 Datasheet, PDF (524/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
11.3.4 Timer Compare Match Clear Register (TCNTCMPCLR)
TCNTCMPCLR is an 8-bit readable/writable register that specifies requests to clear TCNTU_5,
TCNTV_5, and TCNTW_5. The MTU2 has one TCNTCMPCLR in channel 5.
Bit: 7
6
5
4
3
2
1
0
-
-
-
-
-
CMP CMP CMP
CLR5U CLR5V CLR5W
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
7 to 3 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
2
CMPCLR5U 0
R/W TCNT Compare Clear 5U
Enables or disables requests to clear TCNTU_5 at
TGRU_5 compare match or input capture.
0: Disables TCNTU_5 to be cleared to H'0000 at
TCNTU_5 and TGRU_5 compare match or input
capture
1: Enables TCNTU_5 to be cleared to H'0000 at
TCNTU_5 and TGRU_5 compare match or input
capture
1
CMPCLR5V 0
R/W TCNT Compare Clear 5V
Enables or disables requests to clear TCNTV_5 at
TGRV_5 compare match or input capture.
0: Disables TCNTV_5 to be cleared to H'0000 at
TCNTV_5 and TGRV_5 compare match or input
capture
1: Enables TCNTV_5 to be cleared to H'0000 at
TCNTV_5 and TGRV_5 compare match or input
capture
Rev. 4.00 Dec. 15, 2009 Page 464 of 1558
REJ09B0181-0400