SH7080_09 Datasheet, PDF (422/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
(2) Transfer from the normal space interface to the external device with DACK
BSC Register Setting*⁴
Minimum Number of Idle Cycles
CSnWCR.WM Setting CSnBCR Idle Setting
When Access Size is When Access Size is
Greater than Bus
Less than or Equal to
Width*¹
Bus Width*²
1
0
0
2
0
0
1
3
1
1
1
2
0
1
1
3
1
2
2
2
0
2
2
3
1
4
4
4
0
4
4
4
Notes: DMAC is driven by Bφ. The minimum number of idle cycles is not affected by changing a
clock ratio.
1. Minimum number of idle cycles between the word access to address 0 and the word
access to address 2 in the 32-bit access with a 16-bit bus width,
minimum number of idle cycles between the byte access to address 0 and the byte
access to address 1 in the 16-bit access with an 8-bit bus width,
minimum number of idle cycles between the byte accesses to address 0, to address 1,
to address 2, and to address 3 in the 32-bit access with an 8-bit bus width, and
minimum number of idle cycles between consecutive accesses in 16-byte transfer.
2. Other than the above cases.
3. For single address mode transfer from the external device with DACK to the normal
space interface, the minimum number of idle cycles is not affected by the IWW,
IWRWD, IWRWS, IWRRD, and IWRRS bits in CSnBCR.
4. For single address mode transfer from the normal space interface to the external device
with DACK, the minimum number of idle cycles is not affected by the DMAIWA and
DMAIW bits in CMNCR.
5. When the HW[1:0] in the CSnWCR is set to specify 2.5 cycles or more, the number of
idle cycles will be 0.
Rev. 4.00 Dec. 15, 2009 Page 362 of 1558
REJ09B0181-0400