SH7080_09 Datasheet, PDF (234/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.2.1 DTC Mode Register A (MRA)
MRA selects DTC operating mode. MRA cannot be accessed directly by the CPU.
Bit: 7
6
5
4
3
2
1
0
MD[1:0]
Sz[1:0]
SM[1:0]
-
-
Initial value: -
-
-
-
-
-
-
-
R/W: -
-
-
-
-
-
-
-
Initial
Bit Bit Name Value
R/W
7, 6 MD[1:0] Undefined ⎯
5, 4 Sz[1:0] Undefined ⎯
3, 2 SM[1:0] Undefined ⎯
Description
DTC Mode 1 and 0
Specify DTC transfer mode.
00: Normal transfer mode
01: Repeat transfer mode
10: Block transfer mode
11: Setting prohibited
DTC Data Transfer Size 1 and 0
Specify the size of data to be transferred.
00: Byte-size transfer
01: Word-size transfer
10: Longword-size transfer
11: Setting prohibited
Source Address Mode 1 and 0
Specify an SAR operation after a data transfer.
0x: SAR is fixed
(SAR writeback is skipped)
10: SAR is incremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
11: SAR is decremented after a transfer
(by 1 when Sz1 and Sz0 = B'00; by 2 when Sz1 and
Sz0 = B'01; by 4 when Sz1 and Sz0 = B'10)
Rev. 4.00 Dec. 15, 2009 Page 174 of 1558
REJ09B0181-0400