SH7080_09 Datasheet, PDF (345/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
9.5 Operation
9.5.1 Endian/Access Size and Data Alignment
This LSI supports big endian, in which the 0 address is the most significant byte (MSB) in the byte
data.
Three data bus widths (8 bits, 16 bits, and 32 bits) are available for normal memory and SRAM
with byte selection, and two data bus widths (16 bits and 32 bits) are available for SDRAM. For
PCMCIA interface, two data bus widths (8 bits and 16 bits) are available. For MPX-I/O, the data
bus width is fixed at 8 bits or 16 bits, or 8 bits or 16 bits can be selected by the access address. For
burst MPX-I/O, the data bus width is fixed at 32 bits. Data alignment is performed in accordance
with the data bus width of the respective device. This also means that when longword data is read
from a byte-width device, the read operation must be done four times. In this LSI, data alignment
and conversion of data length are performed automatically between the respective interfaces.
Tables 9.17 to 9.19 show the relationship between device data width and access unit.
Table 9.17 32-Bit External Device Access and Data Alignment
Operation
Byte access at 0
Byte access at 1
Byte access at 2
Byte access at 3
Word access at 0
Word access at 2
Longword access
at 0
Data Bus
Strobe Signals
D31 to
D24
D23 to
D16
D15 to
D8
D7 to
D0
WRHH, WRHL, WRH, WRL,
DQMUU DQMUL DQMLU DQMLL
Data 7 to ⎯
⎯
⎯
Assert ⎯
⎯
⎯
Data 0
⎯
Data 7 to ⎯
⎯
⎯
Assert ⎯
⎯
Data 0
⎯
⎯
Data 7 to ⎯
⎯
⎯
Assert ⎯
Data 0
⎯
⎯
⎯
Data 7 to ⎯
⎯
⎯
Assert
Data 0
Data 15 to Data 7 to ⎯
⎯
Assert Assert ⎯
⎯
Data 8 Data 0
⎯
⎯
Data 15 to Data 7 to ⎯
⎯
Assert Assert
Data 8 Data 0
Data 31 to Data 23 to Data 15 to Data 7 to Assert
Data 24 Data 16 Data 8 Data 0
Assert
Assert
Assert
Rev. 4.00 Dec. 15, 2009 Page 285 of 1558
REJ09B0181-0400