SH7080_09 Datasheet, PDF (210/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 7 User Break Controller (UBC)
7.3.11 Break Control Register (BRCR)
BRCR sets the following conditions:
1. Channels A and B are used in two independent channel conditions or under the sequential
condition.
2. A user break is set before or after instruction execution.
3. Specify whether to include the number of execution times on channel B in comparison
conditions.
4. Determine whether to include data bus on channels A and B in comparison conditions.
5. Enable PC trace.
6. Select the UBCTRG output pulse width.
7. Specify whether to request the user break interrupt when channels A and B match with
comparison conditions.
BRCR is a 32-bit readable/writable register that has break conditions match flags and bits for
setting a variety of break conditions.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
UTRGW[1:0] UBIDB - UBIDA -
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R/W R R/W R
Bit: 15 14 13 12 11 10 9
SCM SCM SCM SCM
FCA FCB FDA FDB ^{PCTE PCBA -}
Initial value: 0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R
8
7
6
5
4
3
2
- DBEA PCBB DBEB -
SEQ
-
0
0
0
0
0
0
0
R R/W R/W R/W R R/W R
1
0
- ETBE
0
0
R R/W
Rev. 4.00 Dec. 15, 2009 Page 150 of 1558
REJ09B0181-0400