SH7080_09 Datasheet, PDF (1480/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 28 Electrical Characteristics
Item
Symbol Min.
Max.
Unit Reference Figure
CAS delay time
t
1
CASD
18
ns
Figures 28.24 to
28.40
DQM delay time
t_DQMD
1
18
ns
Figures 28.24 to
28.37
CKE delay time
t
CKED
AH delay time
t_AHD
Multiplexed address delay time t_MAD
Multiplexed address hold time t_MAH
DACK, TEND delay time
t
DACD
1
1/2t_Bcyc + 1
—
1
1
18
ns
1/2t_Bcyc + 18 ns
18
ns
—
ns
18
ns
Figure 28.39
Figure 28.18
Figure 28.18
Figure 28.18
Figures 28.11 to
28.35
FRAME delay time
t_FMD
1
18
ns
Figure 28.19 to
28.22
ICIORD delay time
t_ICRSD
1/2t_Bcyc + 1 1/2t_Bcyc + 18 ns
Figures 28.43,
28.44
ICIOWR delay time
t
ICWSD
1/2t + 1
Bcyc
1/2t + 18 ns
Bcyc
Figures 28.43,
28.44
IOIS16 setup time
IOIS16 hold time
t
IO16S
t_IO16H
1/2t + 13 —
Bcyc
1/2t_Bcyc + 10 —
ns
Figure 28.44
ns
Figure 28.44
Notes: t_Bcyc indicates external bus clock period (Bφ = CK).
1. n denotes the number of wait cycles.
2. If the access time conditions are satisfied, the t_RDS1 condition does not need to be
satisfied.
Rev. 4.00 Dec. 15, 2009 Page 1420 of 1558
REJ09B0181-0400