SH7080_09 Datasheet, PDF (341/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
11
DTBST 0
R/W DTC Burst Enable
Selects whether or not the DTC retains the bus
mastership and remains continuously active until all
transfer operations are complete when multiple DTC
activation requests have been generated.
0: Release the bus on the completion of transfer for each
individual DTC activation source.
1: Keep the DTC continuously active, i.e. only release
the bus on completion of processing for all DTC
activation sources.
Notes: When this bit is set to 1, the following restrictions
apply.
1. Clock setting with the frequency control register
(FRQCR) must be Iφ: Bφ: Pφ: MIφ: MPφ: = 8: 4:
4: 4: 4, 4: 2: 2: 2: 2, or 2: 1: 1: 1: 1
2. The vector information must be in on-chip ROM
or on-chip RAM.
3. The transfer information must be in on-chip
RAM.
4. Transfer must be between the on-chip RAM
and an on-chip peripheral module or between
external memory and an on-chip peripheral
module.
10
DTSA
0
R/W DTC Short Address Mode
In this mode, the information that specifies a DTC
transfer takes up only 3 longwords.
0: Each transfer information is read out as 4 longwords.
The transfer information are arranged as shown in
figure 8.2 (normal address mode).
1: Each transfer information is read out as 3 longwords.
The transfer information are arranged as shown in
figure 8.2 (short-address mode).
Note: Transfer in short-address mode is only available
between on-chip peripheral modules and on-chip
RAM, because the higher-order 8 bits of the SAR
and DAR are considered to be all 1.
Rev. 4.00 Dec. 15, 2009 Page 281 of 1558
REJ09B0181-0400