SH7080_09 Datasheet, PDF (405/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
This LSI
A25 to A0
D7 to D0
D15 to D8
RDWR
CE1A
CE2A
RD
WE
ICIORD
ICIOWR
I/O ports
WAIT
IOIS16
G
G
DIR
G
DIR
G
Card
detector
PC card
(memory or I/O)
A25 to A0
D7 to D0
D15 to D8
CE1
CE2
OE
WE/PGM
IORD
IOWR
REG
WAIT
IOIS16
CD1, CD2
Figure 9.37 Example of PCMCIA Interface Connection
Basic Timing for Memory Card Interface: Figure 9.38 shows the basic timing of the PCMCIA
IC memory card interface. If areas 5 and 6 are specified as the PCMCIA interface, accessing the
common memory areas in areas 5 and 6 automatically accesses the bus with the IC memory card
interface. If the external bus frequency (CK) increases, the setup times and hold times for the
address pins (A25 to A0), card enable signals (CE1A, CE1B, CE2A, CE2B), and write data (D15
to D0) to the RD and WE signals become insufficient. To prevent this error, this LSI enables the
setup times and hold times for areas 5 and 6 to be specified independently, using CS5WCR and
CS6WCR. In the PCMCIA interface, as in the normal space interface, a software wait or hardware
wait using the WAIT pin can be inserted. Figure 9.39 shows the PCMCIA memory bus wait
timing.
Rev. 4.00 Dec. 15, 2009 Page 345 of 1558
REJ09B0181-0400