SH7080_09 Datasheet, PDF (1612/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Connecting crystal resonator .................... 82
Continuous scan mode............................ 962
Control signal timing ............................ 1415
CPU .......................................................... 23
Crystal oscillator....................................... 69
CSn assert period extension.................... 296
Cycle-steal mode .................................... 410
D
Data transfer controller (DTC) ............... 171
Data transfer instructions.......................... 43
DC characteristics................................. 1404
Dead time compensation ........................ 603
Deep software standby mode................ 1341
Direct memory access controller
(DMAC) ................................................. 383
Divider...................................................... 69
DMA transfer by peripheral modules ..... 421
DMA transfer requests............................ 399
DMA transfer types ................................ 406
DTC activation by interrupt.................... 210
DTC activation sources .......................... 184
DTC bus release timing .......................... 206
DTC execution status.............................. 204
DTC vector address ................................ 186
DTC/DMAC activation .......................... 608
Dual address mode.................................. 407
E
Error protection .................................... 1272
Exception handling ................................... 87
Exception handling state........................... 53
External clock input method..................... 83
External pulse width measurement ......... 602
External request mode ............................ 399
External trigger input timing .................. 966
F
Features of instructions............................. 29
Fixed mode ............................................. 402
Rev. 4.00 Dec. 15, 2009 Page 1552 of 1558
REJ09B0181-0400
Flash memory ....................................... 1215
Flash memory characteristics................ 1475
Flash memory configuration ................. 1221
Flash memory emulation in RAM ........ 1274
Flow of the user break operation............. 158
Full-scale error........................................ 969
Function for detecting oscillator stop........ 84
G
General illegal instructions ....................... 98
General registers ....................................... 25
Global-base register (GBR) ...................... 26
H
Hardware protection.............................. 1271
I
I/O ports ................................................ 1161
I²C bus format ......................................... 920
I²C bus interface 2 (I²C2) ........................ 901
Illegal slot instructions.............................. 98
Immediate data formats............................. 29
Influences on absolute accuracy ............. 972
Initial user branch processing time ....... 1281
Initial values of control register ................ 27
Initial values of general register................ 27
Initial values of system register ................ 27
Initiation intervals of user branch
processing ............................................. 1281
Instruction formats.................................... 35
Instruction set............................................ 39
Interrupt controller (INTC) ..................... 105
Interrupt exception handling vector
table......................................................... 123
Interrupt priority ....................................... 96
Interrupt response time ........................... 131
Interrupt sequence................................... 127
Interrupts................................................... 95
IRQ interrupts ......................................... 121