SH7080_09 Datasheet, PDF (233/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.2 Register Descriptions
DTC has the following registers. For details on the addresses of these registers and the states of
these registers in each processing state, see section 27, List of Registers.
These six registers MRA, MRB, SAR, DAR, CRA, and CRB cannot be directly accessed by the
CPU. The contents of these registers are stored in the data area as transfer information. When a
DTC activation request occurs, the DTC reads a start address of transfer information that is stored
in the data area according to the vector address, reads the transfer information, and transfers data.
After the data transfer, it writes a set of updated transfer information back to the data area.
On the other hand, DTCERA to DTCERE, DTCCR, and DTCVBR can be directly accessed by the
CPU.
Table 8.1 Register Configuration
Register Name
Abbrevia-
tion
R/W Initial Value Address
Access Size
DTC enable register A
DTCERA R/W H'0000
H'FFFFCC80 8, 16
DTC enable register B
DTCERB R/W H'0000
H'FFFFCC82 8, 16
DTC enable register C
DTCERC R/W H'0000
H'FFFFCC84 8, 16
DTC enable register D
DTCERD R/W H'0000
H'FFFFCC86 8, 16
DTC enable register E
DTCERE R/W H'0000
H'FFFFCC88 8, 16
DTC control register
DTCCR
R/W H'00
H'FFFFCC90 8
DTC vector base register
DTCVBR R/W H'00000000 H'FFFFCC94 8, 16, 32
Bus function extending register BSCEHR R/W H'0000
H'FFFFE89A 8, 16
Rev. 4.00 Dec. 15, 2009 Page 173 of 1558
REJ09B0181-0400