SH7080_09 Datasheet, PDF (317/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 9 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
20
BEN
0
R/W Burst Enable Specification
Enables or disables 8-burst access to the 16-bit bus
and 16-burst access to the 8-bit bus when 16-byte
access is required. When this bit is cleared to 0, 2-burst
access is performed four times for the 16-bit bus or 4-
burst access is performed four times for the 8-bit bus.
When using a device that does not support 8-burst and
16-burst access, set this bit to 1.
0: Enables 8-burst access to the 16-bit bus and 16-
burst access to the 8-bit bus
1: Disables 8-burst access to the 16-bit bus and 16-
burst access to the 8-bit bus
19, 18 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
17, 16 BW[1:0] 00
R/W Number of Burst Wait Cycles
Specify the number of wait cycles to be inserted
between the second or subsequent access cycles in
burst access.
00: 0 cycles
01: 1 cycle
10: 2 cycles
11: 3 cycles
15 to 13 ⎯
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
12, 11 SW[1:0] 00
R/W Number of Delay Cycles from Address and CSn
Assertion to RD and WRxx Assertion
Specify the number of delay cycles from address and
CSn assertion to RD and WRxx assertion.
00: 0.5 cycle
01: 1.5 cycles
10: 2.5 cycles
11: 3.5 cycles
Rev. 4.00 Dec. 15, 2009 Page 257 of 1558
REJ09B0181-0400