SH7080_09 Datasheet, PDF (270/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
8.6 DTC Activation by Interrupt
The procedure for using the DTC with interrupt activation is shown in figure 8.18.
DTC activation by interrupt
Clear RRS bit in DTCCR to 0 [1]
Set transfer information
(MRA, MRB, SAR, DAR,
[2]
CRA, CRB)
Set starts address of transfer
information in DTC vector table
[3]
Set RRS bit in DTCCR to 1 [4]
Set corresponding bit in
DTCER to 1
[5]
Set enable bit of interrupt
request for activation source [6]
to 1
Interrupt request generated
DTC activated
Determine
clearing method of
activation source
Clear
activation
source
[7]
Clear corresponding
bit in DTCER
Corresponding bit in DTCER
cleared or CPU interrupt
requested
[1] Clearing the RRS bit in DTCCR to 0 clears the read skip flag
of transfer information. Read skip is not performed when the
DTC is activated after clearing the RRS bit. When updating
transfer information, the RRS bit must be cleared.
[2] Set the MRA, MRB, SAR, DAR, CRA, and CRB transfer
information in the data area. For details on setting transfer
information, see section 8.2, Register Descriptions. For details
on location of transfer information, see section 8.4, Location of
Transfer Information and DTC Vector Table.
[3] Set the start address of the transfer information in the DTC
vector table. For details on setting DTC vector table, see section
8.4, Location of Transfer Information and DTC Vector Table.
[4] Setting the RRS bit to 1 performs a read skip of second time or
later transfer information when the DTC is activated consecu-
tively by the same interrupt source. Setting the RRS bit to 1 is
always allowed. However, the value set during transfer will be
valid from the next transfer.
[5] Set the bit in DTCER corresponding to the DTC activation
interrupt source to 1. For the correspondence of interrupts and
DTCER, refer to table 8.2. The bit in DTCER may be set to 1 on
the second or later transfer. In this case, setting the bit is not
needed.
[6] Set the enable bits for the interrupt sources to be used as the
activation sources to 1. The DTC is activated when an interrupt
used as an activation source is generated. For details on the
settings of the interrupt enable bits, see the corresponding
descriptions of the corresponding module.
[7] After the end of one data transfer, the DTC clears the activation
source flag or clears the corresponding bit in DTCER and
requests an interrupt to the CPU. The operation after transfer
depends on the transfer information. For details, see section
8.2, Register Descriptions and figure 8.4.
Transfer end
Figure 8.18 Activation of DTC by Interrupt
Rev. 4.00 Dec. 15, 2009 Page 210 of 1558
REJ09B0181-0400