SH7080_09 Datasheet, PDF (881/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 16 Serial Communication Interface with FIFO (SCIF)
16.3.9 FIFO Control Register (SCFCR)
SCFCR is a 16-bit register that resets the number of data in the transmit and receive FIFO
registers, sets the trigger data number, and contains an enable bit for loop-back testing. SCFCR
can always be read and written to by the CPU.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
RSTRG[2:0]
RTRG[1:0]
TTRG[1:0] MCE TFRST RFRST LOOP
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit Name
15 to 11 ⎯
Initial
value
All 0
10 to 8 RSTRG[2:0] 000
R/W Description
R Reserved
These bits are always read as 0. The write value should
always be 0.
R/W RTS Output Active Trigger
When the number of receive data in the receive FIFO
register (SCFRDR) becomes more than the number
shown below, the RTS signal is set to high.
These bits are valid only when modem control signals
are enabled in asynchronous mode.
000: 15
001: 1
010: 4
011: 6
100: 8
101: 10
110: 12
111: 14
Rev. 4.00 Dec. 15, 2009 Page 821 of 1558
REJ09B0181-0400