SH7080_09 Datasheet, PDF (827/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 15 Serial Communication Interface (SCI)
In clock synchronous serial communication, each data bit is output on the communication line
from one falling edge of the serial clock to the next. Data is guaranteed valid at the rising edge of
the serial clock. In each character, the serial data bits are transmitted in order from the LSB (first)
to the MSB (last). After output of the MSB, the communication line remains in the state of the
MSB. In clock synchronous mode, the SCI transmits or receives data by synchronizing with the
rising edge of the serial clock.
(1) Communication Format
The data length is fixed at eight bits. No parity bit can be added.
(2) Clock
An internal clock generated by the on-chip baud rate generator or an external clock input from the
SCK pin can be selected as the SCI transmit/receive clock. For selection of the SCI clock source,
see table 15.14.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin. Eight clock
pulses are output per transmitted or received character. When the SCI does not perform
transmission or reception, the clock signal remains in the high state. When only reception is
performed, output of the synchronous clock continues until an overrun error occurs or the RE bit is
cleared to 0. For the reception of n characters, select the external clock as the clock source. If the
internal clock has to be used, set RE and TE to 1, then transmit n characters of dummy data at the
same time as receiving the n characters of data.
(3) Transmitting and Receiving Data
SCI Initialization (Clock Synchronous Mode): Before transmitting, receiving, or changing the
mode or communication format, the software must clear the TE and RE bits to 0 in the serial
control register (SCSCR), then initialize the SCI. Clearing TE to 0 sets the TDRE flag to 1 and
initializes the transmit shift register (SCTSR). Clearing RE to 0, however, does not initialize the
RDRF, PER, FER, and ORER flags and receive data register (SCRDR), which retain their
previous contents.
Rev. 4.00 Dec. 15, 2009 Page 767 of 1558
REJ09B0181-0400