SH7080_09 Datasheet, PDF (1326/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 23 Flash Memory
In the above example, the erasing program and programming program are downloaded to areas
excluding addresses (H'FFFFA000 to H'FFFFAFFF) to execute RAM emulation.
Download and initialization are performed only once at the beginning.
In this kind of operation, note the following:
• Be careful not to destroy on-chip RAM with overlapped settings.
In addition to the RAM emulation area, erasing program area, and programming
program area, areas for the user procedure programs, work area, and stack area are
reserved in on-chip RAM. Do not make settings that will overwrite data in these areas.
• Be sure to initialize both the erasing program and programming program.
Initialization by setting the FPEFEQ and FUBRA parameters must be performed for
both the erasing program and the programming program. Initialization must be
executed for both entry addresses: (download start address for erasing program) + 32
bytes (H'FFFF9020 in this example) and (download start address for programming
program) + 32 bytes (H'FFFFB020 in this example).
23.5.3 User Boot Mode
This LSI has user boot mode which is initiated with different mode pin settings than those in user
program mode or boot mode. User boot mode is a user-arbitrary boot mode, unlike boot mode that
uses the on-chip SCI.
Only the user MAT can be programmed/erased in user boot mode. Programming/erasing of the
user boot MAT is only enabled in boot mode or programmer mode.
(1) User Boot Mode Initiation
For the mode pin settings to start up user boot mode, see table 23.1.
When the reset start is executed in user boot mode, the check routine for flash-memory related
registers runs. The RAM area about 1.2 kbytes from H'FFFF9800 and 4 bytes from
H'FFFFAFFC (a stack area) is used by the routine. While the check routine is running, NMI
and all other interrupts cannot be accepted. Neither can the AUD be used in this period. This
period is 100 μs while operating at an internal frequency of 40 MHz.
Next, processing starts from the execution start address of the reset vector in the user boot
MAT. At this point, H'AA is set to the flash MAT select register (FMATS) because the
execution MAT is the user boot MAT.
Rev. 4.00 Dec. 15, 2009 Page 1266 of 1558
REJ09B0181-0400