SH7080_09 Datasheet, PDF (262/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 8 Data Transfer Controller (DTC)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
RW
RW
Vector read
Transfer information
read
Data Transfer information Transfer information
transfer
write
read
Data Transfer information
transfer
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.12 Example of DTC Operation Timing: Chain Transfer
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Clock (Bφ)
DTC activation
request
DTC request
Internal address
R
W
Vector read
Transfer information
read
Data Transfer information
transfer
write
Note: The DTC request signal indicates the state of internal bus request after the DTC activation source has been determined.
Figure 8.13 Example of DTC Operation Timing:
Normal or Repeat Transfer in Short Address Mode
(Activated by On-Chip Peripheral Module; Iφ: Bφ: Pφ =1: 1/2: 1/2;
Data Transferred from On-Chip Peripheral Module to On-Chip RAM;
Transfer Information is Written in 3 Cycles)
Rev. 4.00 Dec. 15, 2009 Page 202 of 1558
REJ09B0181-0400