SH7080_09 Datasheet, PDF (63/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 1 Overview
Items
Specification
On-chip RAM
• 16 kbytes or 32 kbytes
Bus state controller
(BSC)
• Address space divided into nine areas: Eight areas (CS0 to CS7), each
a maximum of 64 Mbytes, and one area (CS8) of a maximum of 1
Gbytes (a total of three areas in SH7083, eight areas in
SH7084/SH7085, and nine areas in SH7086)
• 8-bit external bus
• 16-bit external bus
• 32-bit external bus (only in SH7085/SH7086)
• The following features settable for each area independently
⎯ Bus size (8, 16, or 32 bits)
⎯ Number of access wait cycles
⎯ Idle wait cycle insertion
⎯ Specifying the memory to be connected to each area enables direct
connection to SRAM, SRAM with byte selection, burst ROM (clock
synchronous or asynchronous), MPX-I/O, burst MPX-I/O, SDRAM,
and PCMCIA
• Outputs a chip select signal according to the target area
Direct memory access • Four channels
controller (DMAC)
• External request available
• Burst mode and cycle steal mode
Data transfer
controller (DTC)
• Data transfer activated by an on-chip peripheral module interrupt can
be done independently of the CPU transfer.
• Transfer mode selectable for each interrupt source (transfer mode is
specified in memory)
• Multiple data transfer enabled for one activation source
• Various transfer modes
Normal mode, repeat mode, or block transfer mode can be selected.
• Data transfer size can be specified as byte, word, or longword
• The interrupt that activated the DTC can be issued to the CPU.
A CPU interrupt can be requested after one data transfer completion.
• A CPU interrupt can be requested after all specified data transfer
completion.
Rev. 4.00 Dec. 15, 2009 Page 3 of 1558
REJ09B0181-0400