SH7080_09 Datasheet, PDF (465/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 10 Direct Memory Access Controller (DMAC)
(3) Activation priority when multiple DMAC activation requests are generated
When multiple DMAC activation requests are generated, transfer is performed in the order of
activation priority. However, if multiple DMAC activation requests are generated while the
DMAC is not the bus master, transfer is started for the first activation request. In addition, if
activation requests are generated while the CPU is accessing an external space, transfer is started
for the first activation request and then the second request. Figure 10.5 shows the example of
activation priority operation of the DMAC.
When multiple DMAC activation requests are generated while the CPU is accessing an external space
DMAC is inactive
DMAC is active
Transfer is started for the request that is generated first Transfer is performed according to the priority
Internal bus
Access to external
space by the CPU
DMAC
(CH3)
DMAC
(CH2)
DMAC
(CH0)
DMAC
(CH1)
DMAC CH0 activation request
(Priority: 1)
DMAC CH1 activation request
(Priority: 2)
DMAC CH2 activation request
(Priority: 3)
DMAC CH3 activation request
(Priority: 4)
Priority
determination
When multiple DMAC activation requests are generated while the CPU is not accessing an external space
DMAC is inactive
DMAC is active
Transfer is performed according to the priority
Internal bus
Other than access to
external space by the CPU
DMAC
(CH3)
DMAC
(CH0)
DMAC
(CH1)
DMAC
(CH2)
DMAC CH0 activation request
(Priority: 1)
DMAC CH1 activation request
(Priority: 2)
DMAC CH2 activation request
(Priority: 3)
DMAC CH3 activation request
(Priority: 4)
Priority
determination
Priority
determination
Figure 10.5 Example of Activation Priority Operation of DMAC
(Priority Fixed Mode (CH0 > CH1 > CH2 > CH3))
Rev. 4.00 Dec. 15, 2009 Page 405 of 1558
REJ09B0181-0400