SH7080_09 Datasheet, PDF (635/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Section 11 Multi-Function Timer Pulse Unit 2 (MTU2)
15. Suppressing MTU2–MTU2S Synchronous Counter Clearing
In the MTU2S, setting the SCC bit in TWCR to 1 suppresses synchronous counter clearing
caused by the MTU2.
Synchronous counter clearing is suppressed only within the interval shown in figure 11.62.
When using this function, the MTU2S should be set to complementary PWM mode.
For details of synchronous clearing caused by the MTU2, refer to the description about
MTU2S counter clearing caused by MTU2 flag setting source (MTU2-MTU2S synchronous
counter clearing) in section 11.4.10, MTU2–MTU2S Synchronous Operation.
Tb interval
immediately
after counter
operation starts
Tb interval
at the crest
TGRA_3
TCDR
TGRB_3
Tb interval
at the trough
Tb interval
at the crest
Tb interval
at the trough
TDDR
H'0000
MTU2-MTU2S synchronous counter
clearing is suppressed.
MTU2-MTU2S synchronous counter
clearing is suppressed.
Figure 11.62 MTU2–MTU2S Synchronous Clearing-Suppressed Interval Specified by SCC
Bit in TWCR
Rev. 4.00 Dec. 15, 2009 Page 575 of 1558
REJ09B0181-0400