SH7080_09 Datasheet, PDF (1611/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

Index
A
A/D conversion time............................... 965
A/D converter (ADC) ............................. 945
A/D converter activation......................... 609
A/D converter characteristics................ 1474
A/D converter interrupt source ............... 968
A/D converter start request delaying
function................................................... 592
Absolute accuracy................................... 969
Absolute maximum ratings................... 1403
AC bus timing....................................... 1418
AC characteristics................................. 1411
AC characteristics measurement
conditions.............................................. 1473
Access in view of LSI internal
bus master ............................................... 376
Access size and data alignment .............. 285
Access wait control................................. 294
Address error .......................... 93, 102, 1326
Address map ........................................... 222
Address multiplexing.............................. 305
Addressing modes..................................... 32
Arithmetic operation instructions ............. 45
Asynchronous mode ............... 723, 756, 831
Auto-refreshing....................................... 331
Auto-request mode.................................. 399
B
Bank active ............................................. 323
Basic timing for I/O card interface ......... 349
Basic timing for IC memory card
interface .................................................. 345
Bit synchronous circuit ........................... 941
Block transfer mode................................ 198
Boot mode............................................. 1252
Branch instructions ................................... 49
Break comparison conditions.................. 135
Break detection and processing............... 785
Break on data access cycle...................... 160
Break on instruction fetch cycle.............. 159
Burst mode.............................................. 412
Burst MPX-I/O interface......................... 351
Burst ROM (clock asynchronous)
interface .................................................. 337
Burst ROM (clock synchronous)
interface .................................................. 356
Burst write............................................... 321
Bus arbitration......................................... 370
Bus clock (Bφ) .......................................... 67
Bus mode and channel priority ............... 414
Bus release state ........................................ 53
Bus state controller (BSC) ...................... 217
C
Calculating exception handling
vector table addresses................................ 90
Chain transfer.......................................... 199
Changing frequency .................................. 81
Clock (MIφ) for the MTU2S module........ 67
Clock (MPφ) for the MTU2 module ......... 67
Clock frequency control circuit................. 69
Clock operating mode ............................... 72
Clock pulse generator (CPG) .................... 67
Clock synchronous mode ........ 723, 766, 842
Clock synchronous serial format
(I²C2)....................................................... 930
Clock timing ......................................... 1412
CMT interrupt sources ............................ 981
Compare match timer (CMT) ................. 975
Complementary PWM mode .................. 549
Conflict between NMI interrupt and
DMAC activation.................................... 422
Conflict between NMI interrupt and
DTC activation........................................ 215
Rev. 4.00 Dec. 15, 2009 Page 1551 of 1558
REJ09B0181-0400