SH7080_09 Datasheet, PDF (19/1622 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperH RISC engine Family

15.3.8 Serial Port Register (SCSPTR) ............................................................................. 740
15.3.9 Serial Direction Control Register (SCSDCR)....................................................... 742
15.3.10 Bit Rate Register (SCBRR) .................................................................................. 743
15.4 Operation ........................................................................................................................... 754
15.4.1 Overview............................................................................................................... 754
15.4.2 Operation in Asynchronous Mode ........................................................................ 756
15.4.3 Clock Synchronous Mode..................................................................................... 766
15.4.4 Multiprocessor Communication Function............................................................. 775
15.4.5 Multiprocessor Serial Data Transmission ............................................................. 777
15.4.6 Multiprocessor Serial Data Reception .................................................................. 778
15.5 SCI Interrupt Sources and DMAC/DTC ............................................................................ 781
15.6 Serial Port Register (SCSPTR) and SCI Pins..................................................................... 782
15.7 Usage Notes ....................................................................................................................... 784
15.7.1 SCTDR Writing and TDRE Flag .......................................................................... 784
15.7.2 Multiple Receive Error Occurrence ...................................................................... 784
15.7.3 Break Detection and Processing ........................................................................... 785
15.7.4 Sending a Break Signal......................................................................................... 785
15.7.5 Receive Data Sampling Timing and Receive Margin (Asynchronous Mode) ...... 785
15.7.6 Note on Using DMAC or DTC ............................................................................. 787
15.7.7 Note on Using External Clock in Clock Synchronous Mode................................ 787
15.7.8 Module Standby Mode Setting ............................................................................. 787
Section 16 Serial Communication Interface with FIFO (SCIF) ........................789
16.1 Features.............................................................................................................................. 789
16.2 Input/Output Pins ............................................................................................................... 791
16.3 Register Descriptions ......................................................................................................... 792
16.3.1 Receive Shift Register (SCRSR)........................................................................... 792
16.3.2 Receive FIFO Data Register (SCFRDR) .............................................................. 793
16.3.3 Transmit Shift Register (SCTSR) ......................................................................... 793
16.3.4 Transmit FIFO Data Register (SCFTDR) ............................................................. 794
16.3.5 Serial Mode Register (SCSMR)............................................................................ 794
16.3.6 Serial Control Register (SCSCR).......................................................................... 797
16.3.7 Serial Status Register (SCFSR)............................................................................. 802
16.3.8 Bit Rate Register (SCBRR) .................................................................................. 810
16.3.9 FIFO Control Register (SCFCR) .......................................................................... 821
16.3.10 FIFO Data Count Register (SCFDR) .................................................................... 824
16.3.11 Serial Port Register (SCSPTR) ............................................................................. 825
16.3.12 Line Status Register (SCLSR) .............................................................................. 828
16.4 Operation ........................................................................................................................... 829
16.4.1 Overview............................................................................................................... 829
Rev. 4.00 Dec. 15, 2009 Page xvii of lviii
REJ09B0181-0400